Intel Arrow Lake CPU Architecture To Feature Four Tiles, CPU Tile Includes Coherent Fabric Connecting P-Cores With E-Cores

The CPU layout and architecture of Intel's upcoming Arrow Lake CPUs have been leaked, revealing four tiles in a semi-chiplet package.

Intel's next-generation Arrow Lake CPUs are going to be very different than Lunar Lake CPUs which are primarily designed for the thin and light PC platforms. Targeting the mainstream and high-end PCs, Arrow Lake CPUs will come with enhancements that will push for higher performance and now we have an overview of what the Arrow Lake CPU architecture has to offer under the hood.

Arrow Lake architecture pic.twitter.com/X67rnzrgX3

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So just like Meteor Lake "Core Ultra 100", Arrow Lake "Core Ultra 200" CPUs will feature four main tiles while sitting on a base tile. These tiles include a CPU, SoC, GPU, and IOE Tile. The CPU Tile will feature the latest Lion Cove P-Cores and Skymont E-Cores, coupled with their L2 caches, & a power management unit, and all cores will be connected using a coherent fabric with a shared L3 cache. The Skymont E-Cores won't be the LP-E variants featured on Lunar Lake which not only run at low clock speeds but also feature conservative power limits while eliminating L3 cache. The Lion Cove P-Cores will also be slightly enhanced over the Lunar Lake CPUs, offering faster clocks, and higher IPC improvements.

Intel's Arrow Lake "Core Ultra 200" CPUs will come in various flavors ranging from Arrow Lake-S (Desktop), Arrow Lake-HX (Enthusiast Laptop), Arrow Lake-H (High-End Laptop), Arrow Lake-U (Mainstream Laptop), and Arrow Lake-WS (Xeon Workstation) SKUs. So far, we know about the Intel Arrow Lake 8+16, 6+8, and 2+8 dies but there will be many more based on these three primary configurations. We know that Intel is using TSMC N3B and N6 process node for its Lunar Lake CPU architecture and a Base Tile that uses its own process technology but we can't say for certain if Arrow Lake will go a similar route since the Compute Tile has been rumored to be either 20A or N3B.

Moving over to the GPU Tile, Intel will be offering its latest Xe graphics architecture which has been missing on the high-end platforms. The iGPU will feature up to two GPU slices, a dedicated cache (L3), and a power management unit. Next up is the IOE Tile which will feature a Thunderbolt controller which will enable TBT4/USB4/DP outputs and PCIe lanes.

The biggest slice of the Arrow Lake real estate will likely go to the SoC Tile which will feature several key components such as the memory fabric, memory controller (DDR5/LPDDR5/LPDDR5X), Security Complex, Power Manager, eSPI, a Display Complex, Media Complex, AI Complex, DMI, PCIe, eDP & much more. The SoC Tile will also feature a coherent fabric to connect all controller blocks.

One thing that can be seen across all four tiles is a dedicated D2D "Die-To-Die" interconnect. The Base Tile will be using Foveros packaging technology to connect all chiplets together. Although we are talking about chiplets here, all of the chips will form a singular monolithic package and won't be separate from one another like actual chiplet designs.

Intel's Arrow Lake "Core Ultra 200" CPUs will first debut in Desktop "S" flavors in October. These CPUs will be accompanied by the latest LGA 1851 socketed motherboards using the 800-series chipsets (Z890 first). Expect more information on Intel's Arrow Lake CPUs at the next Innovation event in September.

News Source: @jaykihn0