TSMC Wants To Scale Up Chips Using Bigger Packages As Part of Its System-on-Wafer “SoW” Technology

Well, forget chip shrinking and focus on interposer advancements. TSMC has implemented this by unveiling enormous plans for the next generation of SoW packaging.

Before diving into what TSMC has disclosed, let's talk about interposers. Imagine a chip in your hand. Well, it's a powerful one if you assume it. Now, if you are eager to harness more capabilities out of a single chip, instead of going the innovation route, the industry slaps multiple chips and connects them against each other to achieve cumulative power. To do this, interposers or chip packaging comes in handy. In the era of AI and HPC, where computing power has become more necessary than ever, chip packaging has played a crucial role in taking the industry ahead, and it looks like it will continue to.

At TSMC's Technology Symposium, where the firm showcased its A16 process and revealed plenty of other details, the company did give us a rundown of what to expect with next-gen interposers. Right now, the traditional CoWoS packaging allows the markets to go 3.3x times TSMC's reticle limit. The reticle limit here refers to the multiplier applied to the standard reticle size limitation to determine the effective usable area; in simple terms, the larger the multiplier, the better it is.

Moving to the more interesting part, TSMC has revealed that its upcoming CoWoS-L packaging, which is set to debut by 2026, plans on coming with 5.5x of TSMC's reticle limit, which means that it will feature 12 HBM memory stacks, along with housing a larger substrate, coming at 100×100 mm. With this innovation, the Taiwan giant plans to squeeze out 3.5 times more computing performance than what the previous generation came with, and this is just the start since the firm has bigger plans for the future.

By 2027, TSMC plans to introduce CoWoS with 8x the reticle limit, supporting a larger 120mm x 120mm substrate, integrating four different SoICs, and setting a new tone for the markets to follow. There is also a mention of a dedicated SoW packaging standard as well, which is reported to feature 40 times the reticle limit along with sixty HBM stacks and is explicitly targeted for future data center clusters, which reveals that the future is indeed exciting and SoW, TSMC expects to achieve 40 times the higher performance than modern-day options.

Advancements within chip packaging show that process shrinking isn't the only factor determining the future of computing power. Modern-day developments have already shown us that CoWoS will play a crucial role in shaping the future of the AI and HPC industries.

News Source: Anandtech