TSMC Talks 5nm, 3nm & 12 HBM Stacks In One Package At Tech Symposium

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As it gets thrust right in the center of trade tensions between the United States and China, Taiwanese semiconductor fabrication company TSMC is busy showcasing advanced manufacturing and packaging technologies. In its technology symposium that kicked off at the start of this week, the company announced key details for its semiconductor fabrication techniques and packaging technologies - both of which are slated to play a central role in the current and future tech landscape.

At the symposium, the chipmaker revealed key details for its N5 process node (marketed as 5nm), next-generation interposers that allow for more HBM memory stacks and the N3 process node that will succeed the N5 and be marketed as 3nm.

Starting off with the manufacturing processes, the Taiwanese fab has provided key details for both the 5nm and 3nm nodes. The fab has revealed that 5nm is its highest-quality process node to date when evaluated in terms of defect densities, which for this node are a full quarter ahead than those for its predecessor, the N7. Additionally, TSMC has also confirmed that yields for the process are better than those for N7 and N5, with defect densities also expected to drop at a higher rate than for both the N7 and N10 processing nodes.

As per AnandTech, of all the wafers including and below the 16nm+ process that TSMC will manufacture in 2020, 11% will belong to the 5nm process. This process will be succeeded by the N5P, which will end up improving power consumption by 10% and processing speed by 5%.

The next true node following N5 will be the N3. TSMC has been developing this process for years now, with first reports of the fab's interest in the node having surfaced back in 2016. Now, the fab has provided more details of the node at its symposium and taking a look at them suggests that we're in for quite a treat.

TSMC expects to double and triple producton levels in 2020 in 2021 and 2022 respectively, and the fab also claims that the N3 process node will either improve performance in between 10%-15% or improve power consumption by 25%-30% over the N5 node. Yet, even though TSMC promises that the 3nm process will improve logic gate density by 1.7x, calculations performed by Anandtech reveal. that this will translate into a roughly 26% die shrink owing to the fact that the 1.7x density imporvement will not translate into a similar improvements for SRAM and analog structures.

In addition to revealing key details for the two process nodes, the fab also provided information on improvements in the heavy bandwidth memory (HBM) arena.

In addition to printing chips, TSMC also has the capability to integrate logic dies with memory chips for packages that are stacked in three dimensions. Dubbed as CoWoS-S, this packaging technique also allows for larger HBM stacks, and at the symposium, the fab has revealed that it expects to churn out products that have interposers four times larger than the reticle used to print them and with HBM stacks on board by 2023.

An interposer is a silicon product that is built specifically to connect a memory die to a graphics processing unit chips, and the close proximity between the two that results from an interposer being used results in fewer memory paths between them. A reticle is the part of a lithography machine that consists of the pattern of circuits that are printed on silicon, and generally, the end product is smaller than the reticle.

This, in turn, introduces limits to the maximum size of a chip that can be produced, and TSMC overcomes this limitation by building multiple imposers on a single wafer next to each other and then connecting them later on.