RISC-V Chiplet CPU With 432 Cores To Handle AI & HPC Workloads In Space [UPDATED]

UPDATE 5/11/2023, 7:33 AM CST: This morning, Gianna Paulin, Occamy project lead at the Integrated Systems Laboratory in ETH Zurich, contacted us about the project and several written inaccuracies in the news article. We apologize to Paulin, the Occamy Project group members, and our readers for the incorrect information. The following is their statement from the group's website, explaining the correct information. This can be found on the Occamy project website:

Recently a number of online resources reported on Occamy. While we are happy that our project received some attention, the authors unfortunately, did not check their articles with us, and consequently, there were several factual errors. While the PULP Platform is working towards RISC-V-based systems for space, Occamy specifically was not developed for space, and the ESA was not involved in the development of Occamy. However, we believe that derivatives of Occamy may find applications in Automotive, Avionics, and Space where high performance and extreme energy efficiency are needed and where RISC-V is very rapidly gaining traction. We are also actively looking at options to collaborate with the ESA in future projects.

Occamy is intended as a research vehicle and not an actual product, at least at this stage. It has been taped out in prototyping quantities, and we expect to have some 10s of functional modules at the end. Exact power and performance numbers will certainly be published and made available as soon as we have the assembled modules back, and our estimations suggest that the power will be in the low 10s of Watts range. As this is a research prototype, we will use our characterization laboratory, which is equipped with a temperature-forcing system to provide the necessary cooling and did not engineer a cooling solution.

The Occamy project builds on a large body of work that we have developed over the past 10 years and was supported in part through several national and European projects, including (but not limited to) Oprecomp H2020 - FET Proactive (#732631), European Processor Initiative (EPI) European High Performance Computing JU under FPA (800928) and special grant agreement 101036168, The European PILOT European High-Performance Computing JU under grant agreement 101034126, “Heterogeneous Computing Systems with Customized Accelerators” project that received funding from the Swiss National Science Foundation under grant number #180625. However, Occamy was not designed directly as part of these projects but rather benefited from our involvement in these projects, which resulted in open-source components that we were able to reuse.

We would once again want to highlight the generous support from our industry partners GlobalFoundries, Rambus, Synopsys, Micron, and Avery, without whom this project would have never been possible!

Many enhanced and new IPs were developed for Occamy, but details on these designs, on silicon implementation and measured post-silicon KPIs are still not published. Stay tuned for many exciting news and publications in the next 12 months.

— Occamy Project

ORIGINAL 5/10/2023: The European Space Agency has teamed with researchers at the University of Bologna and ETH Zürich to collaborate on a new RISC-V CPU to increase computational power while in space. The announcement was made during April 2023's Design, Automation, and Test in Europe Conference.

The newly formed project group called the Parallel Ultra Low Power Platform has developed an open-source RISC-V silicon AI chip with tape-outs called Occamy. Occamy will be capable of performing high-performance calculations, increasing efficiency while lowering the time it would take to make these calculations previously.

The design of Occamy has been in development since April 20, 2021, with the first tape out being in July 2022. It features nearly 1B transistors on a 72mm^2, similar to the Sandy Bridge quad-core chip designed by Intel in 2011. The transistor area is placed upon a carrier PCB that measures 52.5 x 45 mm for Fan-Out mounting.

The development is part of the EuPilot program that creates proprietary CPUs to lower the necessity of purchasing chips from manufacturers such as ARM and other x86 chip manufacturers. What is unique about this project is that Occamy utilizes new and older technology in its design.

The memory tile features dual 16 GB HBM2E DRAMs developed by Micron and utilizes 2.5D integration. Since each Occamy dies produces 10 W of power consumption at speeds of 1000 MHz, two Occamy dies, including the HBM2E DRAMs, would increase the total power up to two times. The 32-bit RISC-V control chip maps the data and directs the information to AI cores on the Occamy chip. Occamy has been tested on a single AMD Xilinx Virtex UltraScale+ VCU1525 FPGAs and two Xilinx Virtex UltraScale+ HBMs.

The design of the RISC-V "Occamy" CPU is constructed on the 12nm GlobalFoundry "GF12LPP" process, which consumes low power and is then placed onto a 65nm passive interposer. Occamy utilizes a RISC-V ISA with up to 216 32-bit cores on two chiplets. The total amount of cores available is 432. The performance of the Occamy chip can reach speeds of 0.768 TFLOPs at FP64, 1.536 TFLOPs at FP32, 3.072 TFLOPs at FP16, and 6.144 TFLOPs at FP8 precision when combining the 64-bit Floating Point Units, or FPUS.

The RISC-V chiplet CPU is currently being assembled, and the group is expected to announce more information in the third quarter of this year.

News Sources: Andreas Schilling, HPC Wire