Panmnesia Unveils “CXL Protocol”, Allowing AI GPUs To Utilize Memory From DRAM Or SSDs With Minimal Latency
Panmnesia Unveils “CXL Protocol”, Allowing AI GPUs To Utilize Memory From DRAM Or SSDs With Minimal Latency
Panmnesia, a KAIST startup, has unveiled a cutting-edge IP that enables adding external memory to AI GPUs using the CXL protocol over PCIe, breaking barriers of memory capacities.
Current AI accelerators are confined to onboard memory since manufacturers can only squeeze in a limited amount of HBM. With growing datasets and the need for power, the industry is focusing on racking up more AI GPUs, and the approach isn't sustainable for the longer run when considering the financial and manufacturing resources it takes up. In light of this, Panmnesia, a firm that is supported by the South Korean institute KAIST, has unveiled a CXL IP that can allow GPUs to leverage memory from DRAM or even SSDs, expanding from the in-built HBM.
To bridge the connectivity, CXL utilizes PCIe links, ensuring mass adoption among consumers. However, there's a catch. Traditional AI accelerators lack the necessary subsystems to connect with and utilize CXL for memory expansion directly, and solutions such as UVM ( Unified Virtual Memory) are quite slow, which defeats the purpose in the first place.
However, as a solution, Panmnesia has developed its own CXL 3.1-compliant Root Complex chip, which has multiple ports that connect the GPU to the external memory through a PCIe bus and the HDM (Host-Managed Device Memory) decoder acts as a bridge between the connection, managing memory allocation and translation.
Interestingly, Panmnesia decided to benchmark their solution (CXL-Opt) against prototypes developed by Samsung and Meta, which they have labeled as "CXL-Proto." To our surprise, CXL-Opt achieves a significantly lower round-trip latency, which is the time taken for data to travel from the GPU to the memory and back. CXL-Opt showed a two-digit nanosecond latency while CXL-Proto had 250ns of latency. Apart from that, CXL-Opt's execution time is far less than the UVM solution as it achieves IPC performance speeds 3.22 times more than UVM.
Panmnesia's solution can make massive strides in the markets, as it acts as an intermediary between stacking HBM chips and moving towards a more efficient solution. Given that the company is one of the first ones with an innovative CXL IP, if this gains traction, Panmnesia will benefit significantly.
News Source: Panmnesia
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