Intel Sapphire Rapids ‘4th Gen Xeon’ CPU Delidded By Der8auer, Unveils Extreme Core Count Die With 56 Golden Cove Cores

An Intel Sapphire Rapids '4th Gen' Xeon CPU sample has been delidded by Der8auer, the renowned German overclocker and enthusiast.

This isn't the first time we are looking at a delidded Intel Sapphire Rapids-SP Xeon CPU. In fact, there have been multiple leaks in the past and we even got to see some high-res chip shots straight out of Intel's Arizona fabs where the next-gen server chips are being produced.

Intel Sapphire Rapids Xeon CPU Delidding (Image Credits: Der8auer):

There are several of these chip samples circulating in the online marketplaces (eBay in this case) and this specific variant was the 'Xeon vPRO XCC QWP3'. We can't tell what the exact specifications are for this chip but under the hood, it comes with an Extreme Core Count (XCC) die that features four tiles, each tile with 14 cores and a total of 56 cores on the top-end SKU.

Interesting things that you will notice during the delidding process for the Intel Sapphire Rapids Xeon CPU, as shown in the video, is that the chip features a soldered design and uses high-end liquid-metal TIM with gold plated IHS. The caps on the interposer are also silicone protected to ensure the best thermal performance possible for the Xeon CPUs. Der8auer used his own kit for delidding and it was a simple pop the lid procedure to expose the die (or dies in this case) under the massive IHS.

Intel Sapphire Rapids Xeon CPU Die Shots (Image Credits: Der8auer):

With all four chiplets exposed, we can see that underneath them is a 4x4 (1 IMC tile) core configuration which means each die consists of up to 15 cores. It should be 16 core but 1 of the core area is taken up by the IMC hence we are only left with 15 of the total cores out of which 1 will be disabled for better yields. This means that each die will in fact feature 14 cores for a total of 56 cores per CPU.

According to Intel, the Sapphire Rapids-SP will come in two package variants, a standard, and an HBM configuration. The standard variant will feature a chiplet design composed of four XCC dies that will feature a die size of around 400mm2. This is the die size for a singular XCC die and there will be four in total on the top Sapphire Rapids-SP Xeon chip. Each die will be interconnected via EMIB which has a pitch size of 55u and a core pitch of 100u.

The standard Sapphire Rapids-SP Xeon chip will feature 10 EMIB interconnects and the entire package will measure at a mighty 4446mm2. Moving over to the HBM variant, we are getting an increased number of interconnects which sit at 14 and are needed to interconnect the HBM2E memory to the cores.

The four HBM2E memory packages will feature 8-Hi stacks so Intel is going for at least 16 GB of HBM2E memory per stack for a total of 64 GB across the Sapphire Rapids-SP package. Talking about the package, the HBM variant will measure at an insane 5700mm2 or 28% larger than the standard variant. Compared to the recently leaked EPYC Genoa numbers, the HBM2E package for Sapphire Rapids-SP would end up 5% larger while the standard package will be 22% smaller.

Intel also states that the EMIB link provides twice the bandwidth density improvement and 4 times better power efficiency compared to standard package designs. Interestingly, Intel calls the latest Xeon lineup Logically monolithic which means that they are referring to the interconnect that'll offer the same functionality as a single-die would but technically, there are four chiplets that will be interconnected together. You can read the full details regarding the standard 56 core & 112 thread Sapphire Rapids-SP Xeon CPUs here.