Intel Finally Launches Its 3rd Gen Ice Lake-SP Xeon CPU Lineup: 10nm Server Chips With Up To 40 Cores, 270W TDP, 64 PCIe Gen 4.0 Lanes & More
Intel Finally Launches Its 3rd Gen Ice Lake-SP Xeon CPU Lineup: 10nm Server Chips With Up To 40 Cores, 270W TDP, 64 PCIe Gen 4.0 Lanes & More

Today finally marks the official launch of Intel's 3rd Gen Ice Lake-SP Xeon CPUs which will be the company's first server lineup to be made on the 10nm process node. The Ice Lake-SP lineup aims at the server segment and will be competing against AMD's EPYC Milan family which launched last month.
Starting off with the details, Intel's 3rd Gen Ice Lake-SP Xeon CPUs will be based on the 10nm+ process node and utilize the Sunny Cove core architecture. The Intel Sunny Cove x86 architecture has been around since 2019 and was first featured on Intel's 10th Gen Ice Lake processors for the notebook segment. Intel has since moved over to Tiger Lake which is based on the Willow Cove x86 architecture and makes use of the 10nm SuperFin process node.
Some of the major upgrades that Intel's 10nm+ for Ice Lake-SP Xeon CPU will deliver include:
Some of the major highlights of today's Intel Xeon announcement include:
Intel's Ice Lake-SP will ship in two die configurations, XCC (Extreme Core Count) and HCC (High Core Count). The XCC SKUs will feature 16, 18, 28, 32, 36, 38, and up to 40 cores. The HCC SKUs will feature 8, 12, 16, 18, 20, 24, 26, and up to 28 cores. The TDPs will range from 105, 135, 150, 165, 185, 205, 220, 235, 250, and all the way up to 270W for the flagship SKU. The XCC variants with 32, 36, 38, and 40 cores will be configurated at around 205-270W TDPs.
Intel's Xeon Ice Lake-SP lineup is split between Platinum, Gold, and Silver SKUs. The top SKU is said to be the Xeon Platinum 8380 which would feature 40 cores, a base clock of 2.30 GHz, and a 270W TDP. Compared to AMD's flagship, we are looking at lower cores and a lower base clock however, Intel's architecture and process nodes are tuned for higher clock speeds so that might mark a small win for the blue team. Intel is also placing bets on its AVX-512 instruction set and has shown CPU benchmarks where it handily beats AMD's existing Rome CPUs but only when running applications that fully leverage AVX-512 instructions. Standard applications would not see the same benefit on Intel CPUs.
The Ice Lake-SP CPUs will be supported by the Whitley platform that makes use of the LGA 4189 socket (socket P+). The Whitley platform features 2-way CPU support which will be interconnected with a UPI (Ultra Path Interconnect). The CPUs will be connected to the Intel C620A chipset through DMI & the chipset itself will feature up to 20 PCIe Gen 3 lanes, 10 USB 3.0 ports, and 14 SATA Gen 3 ports. As for the CPUs, they will offer up to 8-channel memory support in DDR4-3200 (1 DPC) or DDR4-2933 (2 DPC) modes. The Ice Lake-SP processors will feature up to 64 PCIe Gen 4.0 lanes.
The 2nd Gen Optane DC Persistent memory would be supported on both platforms (Barlow Pass), offering up to 3200 MT/s and 15% bandwidth improvement in a 15W DIMM. Whitley would be able to support up to 3200 MT/s and 6 TB capacity per socket.
The lineup starts with 8 cores and goes all the way up to 40 cores. The lineup is quite confusing if compared to the AMD EPYC parts so you can see the table below to get a sense of what Intel will be offering in its 3rd Gen Xeon Ice Lake-SP stack:
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