Intel AVX10 ISA To Feature AVX-512 Instructions With Support on Both P-Cores & E-Cores

Intel AVX10 ISA To Feature AVX-512 Instructions With Support on Both P-Cores & E-Cores 1

Intel's upcoming AVX10 ISA (Instruction Set Architecture) has been detailed and comes with AVX-512 support for both P-Cores & E-Cores.

In a slide published by Twitterati, Longhorn, we get to see details of Intel's upcoming AVX10 ISA that seems to be coming in two versions, a pre-enablement (AVX10.1) and a post-enablement (AVX10.2). Both ISAs have one major addition which is support for optional 512-bit FP/int which is something that was excluded from recent client chips. The Intel AVX-512 ISA has been around for a while with Rocket Lake and Tiger Lake but the company decided to disable it from the most recent client-tier chips such as Alder Lake and Raptor Lake.

But it looks like Intel might be bringing these instructions back with processors that support the AVX 10 ISA. According to the pre and post-enablement details, the AVX10 ISA is part of the latest APX (Advanced Performance Extensions) and will offer:

Optional 512-bit FP/int

128/256-bit FP/int

32 vector registers

8 mask registers

256/512-bit embedded rounding

Embedded broadcast

Scalar/SSE/AVX "promotions"

Native media additions

HPC additions

Transcendental support

Gather/Scatter

Version-based enumeration

Support on P-Cores, E-Cores

Now it's not like AVX-512 has entirely disappeared. The support for the instructions still exists on the HPC side with the Xeon chips. However, the client side might just bring AVX-512 instructions back since AMD is already offering it on its Ryzen 7000 consumer processors and they have shown some impressive performance capabilities in specific workloads without taking a big hit on power consumption. Power consumption was a major concern with Intel's previous AVX-512 instructions.

Intel AVX10 represents a major shift to supporting a high-performance vector ISA across future Intel processors. It allows the developer to maintain a single code-path that achieves high performance across all Intel platforms with the minimum of overhead checking for feature support. Future development of the Intel AVX10 ISA will continue to provide a rich, flexible, and consistent environment that optimally supports both Server and Client products.

via Intel

Also, the pre-enablement AVX10.1 version only lists down AVX-512 support for the P-Cores while the AVX10.2 version adds E-Cores too. There were already reports that Intel might be bringing AVX-512 back to client chips in some shape and form in the future. In addition to the previously stated usability benefits, several additional performance-based benefits of Intel AVX10 include:

Intel AVX2-compiled applications, re-compiled to Intel AVX10, should realize performance gains without the need for additional software tuning.

Intel AVX2 applications sensitive to vector register pressure will gain the most performance due to the 16 additional vector registers and new instructions.

Highly-threaded vectorizable applications are likely to achieve higher aggregate throughput when running on E-core-based Intel Xeon processors or on Intel® products with performance hybrid architecture.

> Intel AVX10 includes all the capabilities and features of the Intel AVX-512 ISA, both for processors that feature 256-bit maximum vector register sizes, as well as for processors thatfeature 512-bit vector registers.

Awesome things are on the way ????

— Longhorn (@never_released) July 24, 2023

Granite Rapids on server

— Longhorn (@never_released) July 24, 2023

The company has Meteor Lake for clients, and Granite Rapids & Sierra Forest for its HPC customers. All three families utilize a similar architecture with the P-Cores using Redwood Cove cores and the E-Cores based on the Crestmont architecture. Intel has stated that its future Xeon processors, codenamed Granite Rapids, will be the first to be compatible with AVX10 & will mark the transition from AVX-512 to Intel AVX10 (won't include 256-bit vector extensions). Expect more information in the future.