AMD’s Next-Gen Zen 5 EPYC “Turin” CPUs Pictured: Leak Reveals 128 Core Zen 5 & 192 Core Zen 5C Flavors

AMD 5th Gen EPYC Turin "Zen 5 & Zen 5C" CPU Lineup Leaks Out: Up To 160 Cores, 320 MB Cache & 500W TDP 1

AMD's next-generation EPYC Turin CPUs featuring Zen 5 and Zen 5C architecture in 128-core & 192-core configurations have been leaked.

The latest leak comes from YuuKi_AnS who has not only leaked the first engineering samples of the next-gen AMD EPYC Turin CPUs but also showcased the die configurations that we can expect with these high-performance server chips.

Starting with the details, the AMD EPYC Turin will be the 5th Gen EPYC lineup that replaces the 4th Gen EPYC family. The 4th Gen EPYC family is comprised of Genoa, Genoa-X, Bergamo & Siena CPUs which make use of Zen 4 & Zen 4C cores in EPYC 9004/8004 SKUs. The 5th Gen EPYC family will be similar, featuring a range of configurations and SKUs with Zen 5 "Nirvana" & Zen 5C "Prometheus" cores. The Zen 5 cores are expected to utilize the 3nm process node while Zen 5C may utilize the same or optimized variant.

Based on the images leaked, we are looking at a AMD EPYC "Turin" ES2 chip with a 100-000001245-07 OPN code. This chip was made in 2023 and looks to be very recent. The carrier bracket for AMD Zen 5 Turin-Classic chips seems to be light blue and these chips should retain socket compatibility with the SP5 platform which is designed for the high-end chips. It currently features support for the aforementioned EPYC 9004 lineup.

It should be pointed out that a few months back, the same OPN code was mentioned by Ditto_55. The user also listed various other configurations for the AMD EPYC Turin (internally codenamed as Breithorn) CPU family which include:

100-000001245 - 16 CCD + 1 IOD (128 Zen 5 Core / 256 Thread / 512 MB Cache)

100-000001341 - 12 CCD + 1 IOD (96 Zen 5 Cores / 192 Threads / 384 MB Cache)

100-000001247 - 8 CCD + 1 IOD (64 Zen 5 Cores / 128 Threads / 256 MB Cache)

100-000001342 - 8 CCD + 1 IOD (64 Zen 5 Cores / 128 Threads / 256 MB Cache)

100-000001249 - 2 CCD + 1 IOD (32 Zen 5C Cores / 64 Threads / 64 MB Cache)

Starting with the configurations, the AMD EPYC Turin CPUs with Zen 5 Classic cores will offer up to 128 cores and 256 threads. There will be a maximum of 16 CCDs with 8 cores each, and each CCD will come with its own 32 MB of L3 cache. This will form up to 512 MB of L3 cache. This marks a 33 percent increase in core count and 33 percent increase in the total L3 cache count versus the Zen 4 based EPYC Genoa family.

The IOD will feature a DDR5 integrated memory controller with support for 6000 MT/s speeds, and a PCIe Gen5 (CXL 2.0), Gen3 Infinity Fabric, and Secure Processor support amongst a list of other controllers and accelerators.

The AMD EPYC Turin CPU featuring the Zen 5C cores is where things get crazy with each Zen 5C CCD offering up to 16 cores and 32 MB of L3 cache. There will be twelve compute chiplets onboard these chips for a total of 192 cores and 384 threads with a slightly reduced 384 MB of L3 cache. The CPUs will retain the same I/O as the other classic chips.

Compared to AMD's EPYC Bergamo CPUs based on the Zen 4C cores, the Turin chips with Zen 5C cores will offer a 50% increase in the number of cores and threads (192/384 vs 128/256) while offering the same uplift of 50% in the total cache count (384 MB vs 256 MB). Both Zen 5 & Zen 5C chips are expected to feature TDPs of 480W which can be configured up to 600W. The increase in computing capabilities will mark an incremental path to existing servers who can just drop in these chips on existing platforms and enjoy the added boost.

AMD has so far confirmed that the EPYC Turin CPUs based on the Zen 5 core architecture are on track for launch in 2024 and will deliver a significant jump in performance per watt. The added core counts and improved architecture should help AMD deliver a strong and competitive solution against Intel's Granite Rapids Xeon chips which are also expected to launch in the coming year.