AMD’s 2nd Generation 3D V-Cache Technology Offers Up To 2.5 TB/s Bandwidth
AMD’s 2nd Generation 3D V-Cache Technology Offers Up To 2.5 TB/s Bandwidth
AMD has released additional information regarding its 2nd Generation 3D V-Cache technology featured on the Ryzen 7000 X3D CPUs.
The 2023 International Solid-States Circuits Conference was the second time the company brought information about the new I/O die to light. Website Tom's Hardware received information about the new generation from AMD after @Locuza_ on Twitter revealed the new chipset to the masses:
Zen 4 Raphael 6 nm client I/O die:
- 128b DDR5 PHY + 32b for ECC (8b per 32b channel)- 2x GMI3 Ports, 3x CCDs are not possible. :p- 28x PCIe 5, Zen1/2/3 cIOD had 32x PCIe lanes. So AMD reduced the waste for the client market. - Really just one RDNA2 WGP, 128 Shader "Cores" https://t.co/bkqdVvhgrn pic.twitter.com/erYxTw1p8h
— Locuza (@Locuza_) March 4, 2023
One of the images the company divulged was a first look at the new I/O die for the next generation of its 3D V-Cache. This new I/O die has been featured on the latest Ryzen 7000 X3D "Raphael" CPUs.
AMD will be adding more to the L3 cache versus the non-X3D parts, bringing the size up to 96 MB in one chiplet, and is based on the 7nm process node technology. The L3 cache is stacked upon the 5nm Zen 4 Core Complex Die (CCD). While the next generation will have a smaller cache die, it will keep an identical transistor count. However, the transistor density has increased to 130.6 MTr/mm² from the original 114.6 MTr/mm² and reaches a higher bandwidth of 2.5 TB/s, equalling a twenty-five percent improvement from the 5800X3D design.
The company adjusted the Through Silicon Vias (TSV) connection area by half its size. The CCD from Zen 4 is currently on the Ryzen 7000 X3D consumer processors and EPYC 9004 server/workstation CPUs. Now, the I/O die will be changed for consumer and server models upon release and will have two Global Memory Interconnect ports, eliminating configurations utilizing three CCDs simultaneously.
The new die will also offer 128-bit DDR5 physical layers (PHY) and 32-bit error correction code memory (ECC) with 8 bits per 32-bit channel and twenty-eight times the PCIe 5.0 physical layers, which is four less than the Zen 1/2/3 computation integration on demand, or cIOD. Lastly, the chiplet is expected to offer 128 Shader Cores. You can check more of our coverage of the AMD 7950X3D here.
News Sources: VideoCardz, Locuza_ (Twitter), Tom's Hardware, TechSpot
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