AMD Zen 5 CPU Families Detailed: Granite Ridge Desktop, Fire Range & Strix Halo High-End Laptop, Strix & Krackan For Mainstream

AMD is working on a full stack of Zen 5 "Ryzen" CPU families including Granite Ridge, Fire Range, Strix Halo, Strix & Krackan. These families will target various desktop and mobile platforms with chiplet and monolithic offerings.

It won't be the first time that we have talked about AMD's Zen 5 CPU families featured in the Ryzen segment. We know that the initial round of chips will include a total of five product lineups starting with the highest-end segment which is desktop. A few hours ago, we covered that AMD's Zen 5 core architecture is rumored to feature an IPC improvement of around 10%.

The AMD Granite Ridge and Fire Range CPUs will be very similar to each other. The former is aimed at desktops while the latter is aimed at mobile platforms. Both feature the same Zen 5 dies but in a slightly varied manner since the mobile chips are tuned with conservative power limits in mind. The two Zen 5 families will feature an MCM package with up to two Zen 5 CCDs based on the N4 node & a single Raphael IOD based on the N6 node.

In terms of configuration, both AMD Granite Ridge & Fire Range "Ryzen" CPUs will feature up to 16 Zen 5 cores and 32 threads. Each CCD will retain the 32 MB L3 cache which will be shared with each core and there's also a mention of up to 128 MB of L3 cache (X3D) variants which means we aren't getting dual CCD configurations just yet despite the company having several prototypes of those hidden in the labs.

Ryzen 9000 Desktop CPU Family Highlights:

Other details include the use of two RDNA 3 Compute Units in a single WGP and 28 PCIe 5.0 lanes. It's interesting that RDNA 3 CUs are mentioned instead of RDNA 2. The IOD is supposedly the same as Raphael chips and that packed RDNA 2 CUs. So RDNA 3 might be listed by mistake or we might be looking at a slightly upgraded version of the Raphael iGPU.

Neither the desktop nor laptop SKUs will feature an NPU but they will be supported on existing platforms. For desktops, it's going to be AM5 and motherboard vendors are already rolling out BIOS support. One can also expect better DDR5 memory support in the upcoming Ryzen Desktop lineup.

The AMD Strix Halo APUs will be the chiplet offerings, utilizing up to 3 dies, 2 CCDs, and 1 GCD. The chips will feature up to 16 Zen 5 cores with 32 threads. These chips will retain the same L1 and L2 cache structure so that's a maximum of 16 MB L2 cache while the L3 cache will be increased to 32 MB per CCD. So we can see up to 64 MB of L3 cache on the top (two CCD) chips. The CCDs are said to be different than the ones used on Granite Ridge. Also, only the GCD is mentioned which means that there might be no IOD on board the package.

For the iGPU side, the Strix Halo APUs will retain the RDNA 3+ graphics architecture but will come equipped with 20 WGPs or 40 Compute units. Additionally, to support such high-end iGPUs on a chiplet design, there will also be an additional 32 MB of MALL cache onboard the IOD that will be eliminating bandwidth bottlenecks for this uber iGPU.

Other specifications include support for up to LPDDR5x-8000 (256-bit) memory, and an AI "XDNA 2" NPU capable of delivering over 70 TOPs. The Strix Halo APUs will be centered around the latest FP11 platforms. These APUs will feature TDPs of 70W (cTDP 55W) and will support peak ratings of up to 130W.

AMD Ryzen AI HX Strix Halo Expected Features:

For display, both AMD Strix and Strix Halo APUs will come with eDP (DP2.1 HBR3) and external DP (DP2.1 UHBR10), USBC Alt-DP (DP2.1 UHBR10) and USB4 Alt-DP (DP2.1 UHBR10) support as a part of their media engines. Strix Halo will feature up to DP2.1 UHBR20 support.

The AMD Strix APUs be using the standard monolithic APU design. These chips will be fabricated on the TSMC 4nm process node and will come in SKUs with up to 12 cores and 24 threads. We have seen several engineering samples leak out so far.

As for the cache, the APUs will adopt 12 MB of L2 cache (1 MB per core) and 24 MB of L3 cache which will be partitioned into 8 MB for Zen 5C and 16 MB for Zen 5 cores. The chips will also feature 32 KB of L1 Instruction cache and increase 48 KB of L1 Data cache (32 KB on Zen 4). The APUs will offer 16 PCie Gen 4 lanes.

For memory support, the Ryzen Strix APUs will feature support of up to LPDDR5-7500 & DDR5-5600 memory which is the standard affair for most mainstream laptops. The next-gen Ryzen AI-engine is going to offer up to 50 TOPS (XDNA 2). AMD internally seems to refer to this as AIE2+ or AI Engine 2 Plus.

On the iGPU side, we will see a total of 8 RDNA 3+ WGPs or 16 compute units. We have so far seen this chip clock up to 2.6 GHz in early samples so the final silicon can end up around 3 GHz+. These APUs were once supposedly going to feature 16 MB of MALL cache. All of the AMD Strix Point 1 APUs will be designed around the FP8 socket. It is reported that the Strix APU family will feature TDPs between 45-65W which can be configured down to 28W. Latest details have revealed that the Strix Mono APUs will be branded as the new Ryzen AI HX series with two SKUs mentioned, the Ryzen AI 9 HX 170 which features up to 12 cores, and the Ryzen AI 165 (Non-HX) with up to 10 cores.

AMD Ryzen AI HX Strix Mono Expected Features:

The Kraken (Krackan) Point "Ryzen" APUs will feature 4 Zen 5 and 4 Zen 5C cores for a total of 8 cores and 16 threads. These will be the more mainstream offerings aimed at thin and light designs coupled with a RDNA 3+ GPU architecture (4 WGP / 8 CU). In addition to these, there will be a low-power offering in the form of Sonoma Valley. This chip is likely to power the next-generation Steam Deck & will be featuring just four Zen 5C cores with 8 threads.

AMD is expected to formally announce and unveil its next-gen Zen 5 "Ryzen" CPU portfolio at its Computex 2024 keynote so expect more information in less than a month.

News Source: Golden Pig Upgrade