AMD Unveils Next-Gen EPYC Milan-X CPUs, First To Feature 3D V-Cache Tech With Insane 804 MB Cache

AMD has officially unveiled its first server product to ship with 3D V-Cache technology, the 3rd Gen EPYC Milan-X. The next-generation Zen 3 CPUs retain the outstanding Zen 3 core architecture and further enhance performance in a variety of compute-intensive workloads through increase cache.

The AMD EPYC Milan-X lineup is no mystery, we already saw the chips listed at several retailers & preliminary specifications were listed too. Now we know the exact core clocks and the amount of cache that the new Zen 3 chips with 3D V-Cache vertical chiplets stacking technology will offer for server customers.

AMD EPYC Milan-X server CPU lineup will consist of four processors. The EPYC 7773X features 64 cores and 128 threads, the EPYC 7573X features 32 cores and 128 threads, the EPYC 7473X features 24 cores and 48 threads while the EPYC 7373X features 16 cores and 32 threads. The models along with their OPN codes are:

The flagship AMD EPYC 7773X will rock 64 cores, 128 threads and feature a maximum TDP of 280W. The clock speeds will be maintained at 2.2 GHz base and 3.5 GHz boost while the cache amount will drive up to an insane 768 MB. This includes the standard 256 MB of L3 cache that the chip features so essentially, we are looking at 512 MB coming from the stacked L3 SRAM which means that each Zen 3 CCD will feature 64 MB of L3 cache. That's an insane 3x increase over the existing EPYC Milan CPUs.

The second model is the EPYC 7573X which features 32 cores and 64 threads with a 280W TDP. The base clock is maintained at 2.8 GHz and the boost clock is rated at up to 3.6 GHz. The total cache is 768 MB for this SKU too. Now interestingly, you don't need to have 8 CCDs to reach 32 cores as that can be achieved with a 4 CCD SKU too but considering that you'd need double the amount of stack cache to reach 768 MB, that doesn't look like a very economical option for AMD and hence, even the lower-core count SKUs might be featuring the full 8-CCD chips.

With that said, we have the EPYC 7473X which is a 24 core and 48 thread variant with a 2.8 GHz base and 3.7 GHz boost clock and a TDP of 240W while the 16 core and 32 thread EPYC 7373X is configured at a 240W TDP with a base clock of 3.05 GHz and 3.8 GHz boost clock and  768 MB of cache.

A single 3D V-Cache stack would incorporate 64 MB of L3 cache that sits on top of the TSV's already featured on existing Zen 3 CCD's. The cache will add upon the existing 32 MB of L3 cache for a total of 96 MB per CCD. AMD also stated that the V-Cache stack can go up to 8-hi which means a single CCD can technically offer up to 512 MB of L3 cache in addition to the 32 MB cache per Zen 3 CCD. So with a 64 MB of L3 cache, you can technically get up to 768 MB of L3 cache (8 3D V-Cache CCD stacks = 512 MB) which will be a mammoth increase in cache size.

3D V-Cache could just be one aspect of the EPYC Milan-X lineup. AMD might introduce faster clocks as 7nm continues to mature and we can see much faster performance from these stacked chips. As for performance, AMD showcased a 66% performance uplift in RTL verifications with Milan-X versus the standard Milan CPU. A live demo showcased how Synopsys VCS Functional verification test was completed by Milan-X 16-core SKU much faster than the non-X 16 core SKU.

Some of the highlighted features of the AMD EPYC Milan-X lineup include:

AMD has announced that Milan-X will have broad platform availability through their partners such as CISCO, DELL, HPE, Lenovo, and Supermicro while the launch is planned for Q1 of 2022.