AMD Next-Gen Zen 5 CPUs Rumored To Feature Reworked Cache Design, Larger L2 Cache Per Core

AMD Zen 5 core architecture is rumored to feature a fully reworked cache design which will assist with increasing the IPC for next-gen CPUs.

The rumor comes from AdoredTV who has shared the latest information regarding AMD's next-gen Zen 5 architecture. Although AMD isn't quite done yet with its Zen 4 architecture, the company has the first Zen 5 samples already in labs in early prototypes.

The AMD Zen 5 core architecture which is internally codenamed "Nirvana" has had work started on it since 2020-2021. The first Zen 5 products are expected to land in 2024 & based on recent reports, it will be built completely from the ground up. Since it is a completely new design, the internal CPU architecture is bound to see some major changes, and some possible changes are detailed by tech outlet, AdoredTV.

The first major change rumored for AMD's Zen 5 CPU core architecture is the use of a new "Ladder" shared cache. The earlier Zen architectures had the L3 cache split into two 16 MB blocks shared by the two CCX's within each CCD. Each CCX could only access 16 MB of L3 cache pools.

With Zen 3, AMD change this and dropped the dual CCX to a singular CCX which featured a shared 32 MB L3 cache pool that was connected to all 8 cores within the die in a ring configuration. AMD kept the same design on the Zen 4 chips but with Zen 5, this is rumored to change once again to a new 32 MB L3 "Ladder' cache. This structure is said to drastically reduce the inter-core latency and communication bottlenecks compared to the ring interconnect design. Now the figure shown here is just to provide a visual perspective of how the new L3 cache structure would work & we cannot say for sure if the L3 cache will stick to 32 MB or get a boost.

What is rumored to get a boost is the L2 cache. AdoredTV says that the L2 cache for each AMD Zen 5 CPU core is going to see an uptick. They state that their sources have pointed to AMD having both 2 MB and 3 MB L2 cache per core chips in its labs but they may or may not be Zen 5 parts. In the case that they are Zen 5 chips, this will be a 2x and 3x boost, respectively, over the 1 MB cache per core featured on the existing Zen 4 cores.

This increased cache on the AMD Zen 5 CPU cores can also directly benefit the IPC with a 2 MB L2 cache per core offering up to 4% IPC gains and a 3 MB L2 cache per core offering a 7% IPC gain. The gains are evaluated in multi-threaded workloads and single-threaded workloads might yield a 1% or marginal IPC benefits. Latency will not be affected by the addition of more cache per core as mentioned though all of this is something that needs to be tested and confirmed when the chips launch and that is still a year away from now.

AMD Zen 5 in 2024, Featuring V-Cache & Compute Variants With Brand New Microarchitecture

AMD has so far confirmed that the new Zen 5 architecture will launch in 2024. The Zen 5 CPUs will come in three flavors (Zen 5 / Zen 5 V-Cache / Zen 5C) and the chip itself is designed from the ground up with a completely brand new microarchitecture that focuses on delivering enhanced performance and efficiency, a re-pipelined front-end, and wide issue along with Integrated AI and machine learning optimization. Some of the key features of Zen 5 CPUs include:

While there have been performance, frequency, and power estimates shared by Jim Keller for AMD's Zen 5 CPU core architecture, the design itself is still a mystery for now. The architecture will power more than one CPU family including the Ryzen 8000 "Granite Ridge" for desktops, Ryzen 8000 "Strix Point" & "Fire Range" for Mobile, and EPYC "Turin" for servers next year.