AMD Discloses Zen 4C Architecture Details: Same Design As Zen 4, 35% Smaller, 2x Density & Cores

AMD has further shared details of its Zen 4C core which will feature double the density in a smaller footprint on the EPYC Bergamo CPUs.

In new slides shared by TechpowerUp, we get a taste of what the AMD Zen 4C core architecture is all about. The first slide shows a comparison between all three EPYC 9004 offerings with standard Genoa CPUs used as a reference. The Genoa-X CPUs can be seen to offer higher cache per core & the Bergamo CPUs can be seen to focus more on power efficiency and core density. Higher cores and density on the Bergamo chips are achieved through the integration of Zen 4C cores.

Once again, before we start, I would like to share some of the main features of the AMD Bergamo lineup:

Yesterday, we finally came to learn that the Zen 4C core on the EPYC Bergamo CPUs measures just 2.48mm2 versus the 3.84mm2 of the standard Zen 4 cores. The area includes both the core and its L2 cache. Both Zen 4 and Zen 4C cores are based on TSMC's 5nm process node. Previously, Zen 4C was expected to utilize the TSMC 4nm process node.

AMD managed to fit twice the number of cores and threads with the same L2 cache within a die size that's under 10% bigger than the Zen 4 CCD (72.7mm2 vs 66.3mm2). The Zen 4C CCD which is codenamed "Dinoysus" has an overall -35.4% lower core area and almost every aspect of the CCD has been reduced by -35% to -45%. The full Bergamo chips pack a total of 82 billion transistors on the package.

So coming to the major changes between Zen 4 and Zen 4C on an architectural level, only the L3 cache per core has been reduced from 4 MB per core to 2 MB per core. The rest of the specs are entirely the same and that's a huge deal considering Zen 4C isn't a full-on different architecture from Intel's E-Core and P-Core variations.

You are getting 16 Zen 4C cores within a singular die so that's 128 cores across 8 CCDs. A similar 8 CCD configuration based on the Zen 4 core would feature half the core count at 64. But at the same time, you are getting the same amount of L2 cache of 256 MB as you would get on a 64-core EPYC Genoa chip and since there are four fewer CCDs, AMD can also translate that into higher efficiency.

The Bergamo CPUs are pitted against Intel's E-Core offerings which will arrive next year starting with Sierra Forest which utilizes an Intel 3 process node & an E-core design based on that. Considering that E-Cores don't offer multi-threading and are lacking the same performance as the P-Core offerings, AMD can be very competitive with its current and future Zen Compute-Density offerings.

Besides that, all of the platform specs remain the same with SKU TDPs of up to 400W supported on the existing SP5 (LGA 6096) socket, 12-channel DDR5 EEC memory support (up to 4800 MT/s speed), and up to 12 TB capacities in a dual-socket system (with 256 GB 3DS RDIMMs). The I/O die on EPYC Bergamo CPUs will retain the 160 Gen 5 IO Lanes (2P), 12 PCIe Gen3 lanes, 32 SATA lanes, and 64 IO lanes support for CXL 1.1+. All of the security features such as Secure Boot, SME, SEV-ES, and SEV-SNP are retained.

The AMD EPYC Bergamo CPUs featuring the Zen 4C cores are already shipping to first customers in volume now. The company expects to ramp up by the end of this year.